People

All the members of the Institute for Computing Systems Architecture.

 

Mahesh Marina

 

 

Mahesh Marina

Institute Director

 

Wireless networks, mobile systems, machine learning applications in wireless networks and mobile systems, mobile privacy, network security

Academic Staff

Pramod Bhatotia

Pramod Bhatotia

Systems, Distributed Systems, Operating Systems
Murray Cole
Murray Cole Parallel algorithms, skeletal parallel programming
Christophe Dubach
Christophe Dubach   
Bjoern
Bjoern Franke Software Transformation Driven By Dynamic Information
Boris
Boris Grot Computer architecture, memory systems and interconnection networks. Architectural support for large-scale data processing. Systems with quality-of-service guarantees
Hugh Leather
Hugh Leather

Deep learning for compilers and systems. Energy and performance of data-centres. Mobile systems

Vijay Nagarajan
Vijay Nagarajan General research interests: Software/hardware collaborative techniques for enhancing performance, programmability, reliability and security of parallel architectures. Current research topics: Memory consistency, cache coherence and synchronization for scalable parallel architectures
Mike O'Boyle
Mike O'Boyle  Auto-parallelisation, machine learning based compilation, optimising for heterogeneous multi-cores, GPU optimisation, design space exploration, robotics/vision/deep learning application drivers
Paul Patras
Paul Patras  Performance optimisation in wireless networks, network protocols and architectures, mobile traffic analysis, security and privacy, prototyping and test beds.
  Aaron Smith Post-Moore computing, optimizing compilers, hardware/software co-design, embedded systems, computer architecture, machine learning
Nigel Topham
Nigel Topham  Design and analysis of high-performance computing systems, architecture simulation tools

Associate Members

David Aspinall  

Tariq Elahi

 
Jose Cano Reyes Computer Architecture, Computer Systems, Compilers, Interconnection Networks, Deep Learning
Marcelo Cintra  Computer Architectures, Parallel and High-Performance Computing, Scientific Computing
Chris Fensch The design of many-core architecture and its implications on programability
Jane Hillston  
Paul Jackson  
Markulf Kohlweiss  

Milos Nikolic

 
Ajitha Rajan  
Michel Steuwer  

Research Staff

Roberto Castaneda Lozano Compilers, parallelization, combinatorial optimization, testing and verification
Pavlos Petoumenos Automatically creating representative workloads for designing, training, and evaluating optimisation heuristics
Lu Li Code transformations for high-performance optimizations
Tom Spink  

Honorary Members and Visitors

Dr Gordon Brebner - Honorary Professor
Dr Jose Cano Reyes
Dr Marcelo Cintra - Honorary Professor
Dr Christian Fensch - Honorary Professor
Dr Francisco Garcia - Honorary Professor
Dr Roland Ibbett - Honorary Professor
Dr Michel Steuwer
Dr Harry Wagstaff

Students

Lanre Adeoluwa  
Maurice Bailleu  
Ludovic Capelli Parallel programming. High-performance computing. Vertex-centric graph processing
Bruce Collie Pragmatic program synthesis for improved compiler analysis and optimisation
Lewis Crawford Using compiler optimizations, graphics, and improving performance in real-time rendering systems
Adarsh Doddappagouda Patil Computer architecture and memory systems design
Priyank Faldu Microarchitecture enhancements, simulator design & implementation, workload characterization for bottleneck analysis, debugging performance issues on real hardware, programming parallel softwares, accelerating applications using GPU via OpenCL/CUDA etc.
Yini Fang  
Vasileios Gavrielatos  
Dimitra Giantsidi  
Philip Ginsbach  
Adam Harries  
Vikto Ivanov  
Maurice Jamieson

Use of micro-core architectures for High-Performance Computing (HPC) and embedded applications, with a focus on programmability in terms of design (kernel offload abstractions) and implementation (compiler and runtime techniques)

Kuba Kaszyk Fast and Accurate GPU Simulation
 Siavash Katebzadeh Computer Architecture, Compilers and the use of the graphics processing unit (GPU) as a general purpose processor. Currently I am working on Network Topologies, Routing and Congestion Control with particular emphasis on Predictable Datacenters
Antonis Katsarakis

Distributed Systems & Data Replication

Caner Kilinc Data driven applied Machine Learning and Artificial Intelligence in 5G Automation
Martin Kristien Cross-architecture simulation of multi-core systems
Zhibo Li  
Haoyu Liu  
Martin Lucke  
Aleksandr Maramzin  
Artemiy Margaritov  
Paul Metzger

Pattern Based Parallel Programming Language Models, Schedulers for Heterogeneous and Homogeneous Systems

Rupen Mitra Networked systems, Mobile Networking, Network Security
Naums Mogers Computational optimisation of Neural Networks, rewrite rules-based compilation, GPGPU
Paschalis Mpeis

Personalized optimization for interactive mobile applications. It uses a transparent approach that captures user inputs and replays them afterwards to apply offline iterative compilation

Vito Nordloh Optimising compilers
Martynas Noreika  
Nicolai Oswald  
Christos Perivolaropoulos  
Federico Pizzuti  
Rodrigo Rocha Optimising compilers, compiler construction, parallel programming for heterogeneous architectures, and energy-aware high-performance computing
Martin Ruefenacht  
Heba Salem  
Christof Schlaak Optimising compilers, HPC, hardware design, machine learning
Amna Shahab Computer architecture, memory systems, architectures for emerging datacenter workloads, large-scale training of deep neural networks
Rajkarn Singh Mobile network data analytics, 5G network architecture, machine learning for network optimization, privacy preserving data publishing
Larisa Stoltzfus Performance portability, HPC, 3D wave models
Christodoulos Stylianou  
Chuanhao Sun  
Jorg Thalheim  

Jack Turner

Hardware aware compilation of deep learning models for embedded systems
Dmitrii Ustiugov  Crossroads of Computer Systems and Computer Architecture with a focus on hardware and AI support for cloud infrastructure
Christos Vasiladiotis Interest is the automatic compiler parallelization of legacy software and its further promotion to structured parallel patterns, with a focus on loop level parallelism
Jackson Woodruff Using the compiler to manage reconfigurable hardware
Justs Zarins research interests are in asynchronous algorithms, tasking parallelism and application runtime and performance visualisation
Chaoyun Zhang Deep learning, mobile networking, spatio-temporal data mining
Mingcan Zhu Memory systems for data centres, Processor architecture and micro-architecture

Administration

Nina Abbott-Barish Finance Administrator
Jodie Cameron Institute Administrative Assistant
Joanne Pennie Portfolio Manager
Steph Smith Insitute Administrator

Commercialisation

Keith Edwards (Senior Business Development Executive)