All the members of the Institute for Computing Systems Architecture.


Mahesh Marina



Mahesh Marina

Institute Director


Wireless networks, mobile systems, edge/cloud computing, applied machine learning, network security and privacy

Academic Staff

Ross Anderson
Ross Anderson Security engineering; adversarial machine learning; security economics and psychology; the measurement of cybercrime and abuse; surveillance and privacy.
Antonio B ICSA
Antonio Barbalace

Systems Software (hypervisor, operating systems, runtime, compiler and linker) for parallel, distributed and heterogeneous computer architecture (including near data processing platforms)

Real-time and general-purpose scheduling, targeting large deployments (data-center) as well as small-devices (embedded/IoT)

Murray Cole
Murray Cole Parallel algorithms, skeletal parallel programming
Bjoern Franke Software Transformation Driven By Dynamic Information
Tobias Grosser ICSA
Tobias Grosser Compiler Optimization, Loop Optimization, High-Performance Computing, Linear Programming Solvers, Climate Modeling, Hardware Design Languages, Programmer Productivity, Domain-Specific Compilation, Programming Languages
Boris Grot Computer architecture, memory systems and interconnection networks. Architectural support for large-scale data processing. Systems with quality-of-service guarantees
Michio Honda
Michio Honda System Software for Networking, Systems for Machine Learning, Internet Architecture and Datacenter Systems
Hugh Leather
Hugh Leather

Deep learning for compilers and systems. Energy and performance of data-centres. Mobile systems

Luo Mai
Luo Mai Computer Systems and Networking, Distributed Machine Learning, Big Data Processing, Cloud-Edge AI Systems
Vijay Nagarajan
Vijay Nagarajan Software/hardware collaborative techniques for enhancing performance, programmability, reliability and security of parallel architectures.  Memory consistency, cache coherence and synchronization for scalable parallel architectures
Mike O'Boyle
Mike O'Boyle  Auto-parallelisation, machine learning based compilation, optimising for heterogeneous multi-cores, GPU optimisation, design space exploration, robotics/vision/deep learning application drivers
Paul Patras
Paul Patras  Artificial intelligence in mobile networks, traffic analytics, performance optimisation, security and privacy, prototyping and test beds
Amir - ICSA
Amir Shaikhha domain-specific languages, databases, programming languages, compilers
Michel Steuwer ICSA
Michel Steuwer Areas of interest: Compilers, intermediate representations, programming languages, structured parallel programming, heterogeneous and GPU computing, performance portability, novel compilation techniques for high-level languages
Nigel Topham
Nigel Topham  Design and analysis of high-performance computing systems, architecture simulation tools

Associate Members

David Aspinall Computer security (particularly proof-carrying code), type systems for specification and programming languages, and proof development environments

Tariq Elahi

Computer and network security and privacy enhancing technologies (PETs) with an emphasis on effective, efficient, and robust deployments
Vashti Galpin

Formal modelling and simulation of micro-architecture security

Jane Hillston Quantitative analysis and verification supported by formal methods: stochastic process algebras, stochastic logic, Markov processes, continuous approximations, performance modelling, systems biology, collective adaptive systems
Paul Jackson Formal verification of hardware, software and cyber-physical systems. Formalised mathematics. Automation of formal reasoning
Elham Kashefi Models of quantum computing and their structural relations, exploring new applications, algorithms and cryptographic protocols for quantum information processing device.
Markulf Kohlweiss Foundations of cryptography, formal verification, and applied cryptography

Milos Nikolic

Database management systems, in-database learning, large-scale data analytics, stream processing
Ajitha Rajan Software engineering, challenges in software testing

Research Staff

  Sukarn Agarwal  
  Waleed Ahsan  
  Rodrigo Caetano De Oliveira Rocha  
  Andres Goens  
  Luc Jaulmes  
   Tobias Kohn  
  Adel Sefiane  
Volker Seeker
Volker Seeker Energy efficient mobile computing, scheduling for heterogeneous systems, parallel programming pattern, and compiler optimisation  
  Christos Vasiladiotis  
  Yuan Wen  

Honorary Members

Pramod Bhatotia Systems, Distributed Systems, Operating Systems
Prof.  Gordon Brebner  
Prof. Marcelo Cintra Computer Architectures, Parallel and High-Performance Computing, Scientific Computing
Dr Christophe Dubach  
Dr Christian Fensch The design of many-core architecture and its implications on programability
Prof. Francisco Garcia  
Prof. Roland Ibbett  
Dr Pavlos Petoumenos Automatically creating representative workloads for designing, training, and evaluating optimisation heuristics
Aaron Smith Post-Moore computing, optimizing compilers, hardware/software co-design, embedded systems, computer architecture, machine learning


Sam Ainsworth
Sam Ainsworth Computer architecture, optimising compilers, architectural and programming language security, memory systems, memory-level parallelism, fault tolerance
  Dr Jose Cano Reyes Computer Architecture, Computer Systems, Compilers, Interconnection Networks, Deep Learning
  Roberto Castaneda Lozano Compilers, parallelization, combinatorial optimization, testing and verification


Lanre Adeoluwa  
Shinichi Awamoto  
Maurice Bailleu  
Shrey Bhardwaj  
Ludovic Capelli  
Bruce Collie  
Lewis Crawford  
Andrew David  
Adarsh Doddappagouda Patil Computer architecture and memory systems design
Yini Fang  
Vasili Gavrielatos Consistency enforcement in distributed systems (aka replication protocols) amd multiprocessors (aka coherence protocols)
Dimitra Giantsidi  
Celeste  Hollenbeck  
Maurice Jamieson

Use of micro-core architectures for High-Performance Computing (HPC) and embedded applications, with a focus on programmability in terms of design (kernel offload abstractions) and implementation (compiler and runtime techniques)

Kuba Kaszyk Fast and Accurate GPU Simulation
 Siavash Katebzadeh Computer Architecture, Compilers and the use of the graphics processing unit (GPU) as a general purpose processor. Currently I am working on Network Topologies, Routing and Congestion Control with particular emphasis on Predictable Datacenters
Caner Kilinc Data driven applied Machine Learning and Artificial Intelligence in 5G Automation
Amir Khordadi  
Mark Klaisoongnoen  
Martin Kristien Instruction set simulation for multicore systems
Jon Larrea Martinez Mobile networks, networking systems and operating systems
Zhibo Li Data-Centric parallelisation
Haoyu Liu  
Nikolaos Louloudakis  
Martin Lucke  
Karim Manaouil  
Artemiy Margaritov  
Nikos Mavrogeorgis  
Rupen Mitra Networked systems, Mobile Networking, Network Security
Naums Mogers Compilation with machine learning-driven automatic parallelization targeting heterogeneous multi-core platforms such as CPUs, GPUs and FPGAs
Paschalis Mpeis

Personalized optimization for interactive mobile applications. It uses a transparent approach that captures user inputs and replays them afterwards to apply offline iterative compilation

Martynas Noreika  
Nicolai Oswald  
Christos Perivolaropoulos  
Federico Pizzuti  
Xueying Qin  
Rodrigo Rocha  
Heba Salem  
David Schall  
Christof Schlaak Optimising compilers, HPC, hardware design, machine learning
Amna Shahab Computer architecture, memory systems, distributed machine learning
Dimitrios Stavrakakis  
Larisa Stoltzfus HPC, code generation, compilers, stencils, scientific computing
Christodoulos Stylianou  
Chuanhao Sun  
Jakub Szewczyk  
Jorg Thalheim  
Jack Turner  
Dmitrii Ustiugov  Crossroads of Computer Systems and Computer Architecture with a focus on hardware and AI support for cloud infrastructure
Christos Vasiladiotis Interest is the automatic compiler parallelization of legacy software and its further promotion to structured parallel patterns, with a focus on loop level parallelism
Chad Verbowski  
Tongjie Wang  
Mahesh Wickrama Arachchilage  
Jackson Woodruff Using the compiler to manage reconfigurable hardware
Tong Xing  
Leyang Wue  
Justs Zarins  
Mingcan Zhu  


Craig McKenzie Smith Finance Administrator
Vacancy  Institute Administrative Assistant
Ruta Bader Portfolio Manager
Steph Smith Institute Administrator


Keith Edwards Senior Business Development Executive