Two ICSA papers at the prestigious International Symposium on Computer Architecture

Two papers from ICSA researchers have been accepted for presentation at The 45th International Symposium on Computer Architecture (ISCA), the premier venue for computer architecture research.

ISCA Conference 2018

Many congratulations to the (overlapping) teams behind the two papers which have selected to appear at ISCA, and in particular to Vijay Nagarajan, the author-in-common! The papers are:

ProtoGen: Automatically Generating Directory Cache Coherence Protocols from Atomic Specifications automates the design of cache coherence protocols. Cache coherence protocols are hardware communication protocols that keep the caches of multicores consistent. These are notoriously hard to design and verify, yet subtle bugs can seriously affect end users;  for example, a bug in the cache coherent interface caused the Samsung Galaxy S4 to ship with coherence disabled, with serious performance/power implications. ProtoGen is an important step towards correct-by-construction coherence protocols. This is the joint work of ICSA researchers: Nicolai Oswald and Vijay Nagarajan; and Daniel Sorin (who is on a sabbatical here at Edinburgh).  A copy of the paper can be found here

DHTM: Durable Hardware Transactional Memory is the first practical proposal for achieving ACID transactions in hardware. Transactions are a powerful programming idiom that have found widespread adoption. First pioneered in databases, they satisfy ACID -- i.e. actions within a transaction are Atomic, Consistent, Isolated and Durable. Transactions have now been applied in other contexts, most notably for easing parallel programming complexity. In fact, todays processors provide support for hardware transactions, but suffer from two limitations. First, they satisfy only atomicity, consistency and isolation but not durability (A, C and I but not D); second, the size of the transactions are limited by the size of the level-1 hardware cache.  DHTM overcomes these limitations by exploiting new persistent memory technologies (that are both non-volatile and fast) to support ACID efficiently in hardware. This is the joint work of Arpit Joshi, Vijay Nagarajan, Marcelo Cintra  and Stratis Viglas.  A copy of the paper can be found here