ICSA Researchers - Finalists For Award For Work on Next-Generation Memories
The Memorable Paper Award recognizes the best recent research on non-volatile memories published throughout the world.
Arpit Joshi and a team of The University of Edinburgh researchers are finalists for the 2018 Memorable Paper Award for System Architecture and Applications at the 9th Annual Non-Volatile Memories Workshop (NVMW) hosted by the University of California, San Diego.
Their paper, "Architectural Support for Atomic Durability in Non-Volatile Memory" was one of six finalists for the award selected from over 80 papers submitted to the workshop. A full citation for their work and a summary is below. A. Joshi, V. Nagarajan, S. Viglas, and M. Cintra ATOM: Atomic Durability in Non-volatile Memory through Hard- ware Logging, in HPCA, 2017
Modern computer systems consist of two separate tiers to maintain data. The fast but volatile memory tier (RAM) maintains data that programs can directly access. The slow but durable storage tier (SSD, HDD etc.) maintains data that is durable across system restarts. The significant performance difference between these tiers meant that durability was extremely slow and costly. Persistent memory technologies like 3D XPoint are on the horizon which combine the durability property of storage with low latency of memory -- fast persistent (non-volatile) memory. This can provide extremely fast durability which has the potential to speed up many applications like online banking and e-commerce. However, in the absence of appropriate support from the system, an application interrupted by a power failure could corrupt the durable data in persistent memory. This is because data tends to be cached in much faster but volatile memories (caches) and is not necessarily available in memory in a consistent state. For example, consider a system that is executing a banking transaction which consists of debiting money from account A and crediting it to account B. If a power failure happens while this transaction is executing, then it is possible that money is debited from account A but not credited to account B. To avoid such scenarios, persistent memory systems need to provide primitives that would keep all the data in persistent memory in a consistent state. In this instance, a primitive called Atomic Durability is required which guarantees that either all updates are performed or none are performed. For the same example of banking transaction discussed earlier, if the system supports atomic durability, it will guarantee that either the money is debited from A and credited to B, or it is neither debited from A nor is it credited to B. Applications typically update data in low latency caches and allow it to trickle down to memory, which has relatively higher latency, asynchronously in the background. However, atomic durability enforces an order in which updates can reach persistent memory. Therefore, supporting it in software has poor performance as the application is always waiting for an update to reach persistent memory before performing the next update. We propose ATOM, which provides hardware support for atomic durability in persistent memory. ATOM allows applications to continue writing updates to low latency caches and enforces the necessary ordering requirements of atomic durability asynchronously in the background. ATOM also significantly reduces the programming effort by relieving the programmer of all the crash consistency related effort by just demarcating the region of code that needs to be made durable atomically. ATOM leverages the existing memory system design of a processor to provide support for atomic durability. A key feature proposed by ATOM is to make a small part of the memory controller persistent. In fact, Intel has implemented a similar feature for supporting crash consistency. In summary, ATOM is a practical solution for atomic durability which not only provides significant performance improvement but also eases the burden of writing crash consistent programs.
About The Memorable Paper Award
The Memorable Paper Award recognizes the best recent research on non-volatile memories published throughout the world. It is given annually to outstanding research published in the last two years that is expected to have substantial impact on the study of non-volatile memories. To be eligible, the paper must have been published in peer-reviewed venue in the last two years and the lead researcher must have been a student at the time.
About the Non-Volatile Memories Workshop
The Non-Volatile Memories Workshop is the world's premier venue for research into how to use non-volatile memory technology to improve the performance, reliability, and efficiency of computing systems. It was founded in 2010 by Dr. Paul Siegel and Dr. Steven Swanson of the University of California, San Diego's Jacob School of engineering. The workshop is a co-production of the Center for Magnetic Recording Research (http://cmrr.ucsd.edu) and the Non-Volatile Systems Laboratory (http://nvsl.ucsd.edu) at UC San Diego.
More information, including a detailed program, is available at http://nvmw.ucsd.edu.